As it is well known, in such applications as motor control, the power devices employed must be suitable to withstand the energy stress that originates from a short-circuit situation, or more generally, from a fault condition of the system which comprises power devices over a time period that may be on the order of tens of microseconds.
Accordingly, these power devices must be strong throughout this time period in order to give appropriate protection circuits a chance to remove the faulty condition and block the system operation.
Particularly interesting is the “Fault Under Load” (FUL), i.e. short-circuit, occurring during the conductive step during which the power device undergoes high current peaks.
Examples of standard power devices include MOS power transistors and IGBTs. For simplicity, reference will be made hereinafter to a power device obtained by means of an IGBT, and having gate, emitter and collector terminals, the considerations thereon being equally applied to a MOS power transistor and having corresponding gate, drain and source terminals.
FIG. 1 schematically shows a circuit configuration 1 useful for completely testing (FUL TEST) power devices.
In particular, the circuit configuration 1 comprises a first power device QF, especially an IGBT transistor, connected between a power switch SWITCH and a reference potential GND by means of its collector and emitter terminals, CF, and EF.
The power switch SWITCH is connected in turn between a voltage reference Vbus and the power device QF, and is parallel connected to an inductive load LOAD.
Under normal operation condition on the inductive load LOAD, the power switch SWITCH is turned on to short-circuit the inductive load LOAD and raise the collector voltage CF of the power device QF to the level of the voltage Vbus.
It should be noted that the power device QF has a capacitance CGC, known as Miller capacitance, connected between the collector terminal CF and a gate terminal A, as well as a gate capacitance CGE connected between the gate terminal A and the emitter terminal EF.
Consider the following comprehensive relation:
                    i        =                  C          ·                                    ⅆ              V                                      ⅆ              t                                                          (        1        )            where i is the current flowing through a capacitance C, and dV/dt is the timing voltage variation across the capacitance C. It can be appreciated that the quick variation of the collector voltage CF generates a current ICG through the Miller capacitance CGC, this current causing a raise in the voltage VGE on the gate terminal A and, as a consequence, an increase of the saturation current IC of the power device QF, as shown in FIG. 2.
As a peak value is attained, the collector CF current IC goes down, thus causing the collector voltage VCE to overshoot because of parasitic inductances of the Vbus-to-collector CF path.
The collector CF voltage VCE will eventually settle at the Vbus value, and the current IC attains a steady state value given the following relation:IC=(1+β)gm(VGE−VTH)  (2)where: β is the current gain of the intrinsic PNP transistor of the device QF obtained by means of an IGBT transistor; and gm, VGE, and VTH are the transconductance gain, the gate terminal A voltage and the threshold voltage of the intrinsic MOS of the IGBT device, respectively.
Under such conditions, the energy stress undergone by the power device QF is augmented by the high peak of current IC, being, in this instance, three times higher than the steady-state value of current in the short-circuit mode.
Tests carried out by the Applicant have shown, with respect to a peak-less transient, an increase of 10 to 15% in energy dissipation and that this percentage can be even higher if considering increasing resistance values.
The waveforms shown in FIG. 3 illustrate the effect of increased resistance RG of the gate A on the peak of the collector CF current IC: a higher gate A resistance RG produces a higher peak of voltage VGE, resulting in longer decay time for the gate A voltage VGE, until the value of voltage VGE is reached, corresponding to an output voltage of a driving circuit necessary to drive the power device QF. This causes the voltage VGE of gate A to be more easily affected by variations of the voltage VCE at the collector CF. The result is a further increased value of the gate A voltage VGE and, as a consequence, increased peak of current IC of collector CF.
In certain applications, for example, to reduce electromagnetic emissions (EMI) from high switching speeds, it is common practice to slow the switchover down by using gate resistances RG of 100 to 150 Ohms, which force a FUL-faulted power device QF to conduct high current peaks (of 250 to 300 A in FIG. 3). In addition, excessive overshooting of the gate A voltage VGE may cause the gate oxide of the power device QF—which may have been rated for 20 to 40 V—to collapse.
Thus, the aim is that of limiting the current peak that originates, under FUL situation, by means of a suitable protection circuit.
A first prior art solution for limiting the current IC peak of the collector CF when in a fault situation—hereinafter also indicated as the “fault current”—is that of using a protection circuit connected between the power device and a driving device, which reduces the gate resistance of the power device.
Shown in FIG. 4 is a circuit configuration for driving power devices QA of the type comprising a protection circuit according to the prior art.
In particular, the circuit configuration 1A comprises a first power device QA connected between a load and a voltage reference, specifically a ground reference GND. This power device QA has a gate terminal GA connected to an output TA of a driver 2A through a protection circuit 3A.
In the example shown, the driver 2A conventionally comprises the series of two complementary bipolar transistors having their relevant collector terminals connected to the ground reference GND and to a second voltage reference which may be the supply voltage Vcc. These transistors have their emitter terminals connected together to the output terminal TA of the driver 2A.
Furthermore, the base terminals of the transistors comprised in the driver 2A are connected together and to the input terminal of the driver 2A itself through an auxiliary resistance.
The protection circuit 3A comprises a resistance RGA connected between the driver 2A and the power device QA, and comprises a diode D parallel connected with said resistance RGA between the gate terminal GA of the power device QA and the output terminal TA of the driver 2A.
In order to limit the increase of voltage at the gate terminal GA of the power device QA due to the current ICG, the gate terminal impedance between the collector and gate terminals CA and GA of the faulted power device QA is reduced. The current ICG flowing through the Miller capacitance encounters, along the gate path, less resistance, and therefore, a lower voltage is produced across the resistance RGA.
Although advantageous from several points of view, this first solution has several drawbacks.
In particular, to provide the low-impedance path on the resistance RGA in a fault situation, a diode D has to be parallel connected with the gate resistor RGA. But the diode D will be operative each time that the power device QA is turned off, so that the switching speed of the power device QA cannot be controlled by sizing the gate resistance RGA.
A second circuit configuration for driving power devices and limit the current IC peak of the collector CF due to a fault condition is shown in FIG. 5.
For clarity, elements being identical as for structure and function with respect to the circuit configuration shown in FIG. 4 have been indicated with the same reference numerals and no further described.
In particular, the circuit configuration 1B of FIG. 5 includes a protection circuit 3B between the power device QA and a driver 2A that is used for clamping the gate voltage fixing it at 15 V.
The protection circuit 3B comprises a resistance RGA connected between the driver 2A and the power device QA, and a diode D1 connected between the gate A terminal GA of the power device QA and a voltage reference clamped at 15 V.
As the gate voltage of the power device QA begins to rise due to a FUL situation, some of the gate current is diverted off the path that contains the gate resistance RGA through the diode D1, so that the gate voltage is held at 15 V.
A third circuit configuration for driving power devices, which is effective to limit the fault current, is shown in FIG. 6.
In particular, the circuit configuration 1C of FIG. 6 includes a protection circuit 3C between the power device QA and a driver 2A that is used for clamping the gate voltage.
The protection circuit 3C comprises a gate resistance RGA connected between the driver 2A and the power device QA, and a series of a diode D2 and a Zener diode D3 connected between the gate terminal GA and a ground reference GND.
As the gate voltage of the power device QA begins to rise due to a FUL situation, some of the gate current is diverted off the path that contains the resistance RGA through the series of diodes D2 and D3, so that the gate voltage is set by the inverse voltage of the Zener diode D3, which is selected higher than the drive voltage value of the gate terminal GA in a normal operation condition.
While achieving their objectives, also these two prior art solutions acting to clamp the gate voltage have drawbacks.
In fact both protection circuits 3B and 3C of FIGS. 5 and 6 will clamp the value of the gate voltage VGE on the occurrence of a fault. In this way, although limiting the dynamic increase of the gate voltage and hence of the fault current, these circuits reduce the overall effectiveness of the protection device.
There is a need for a protection device effective to limit the leakage currents through the circuit on the occurrence of a fault, which would ensure reliable operation under all conditions. Such a device typically has appropriate structural and functional features so as to leave the switching dynamics unaffected, and in this way overcome the limitations of prior art circuits.